3rd Workshop on Democratizing Domain-Specific Accelerators (WDDSA 2024)

In conjunction with the 57th IEEE/ACM International Symposium on Microarchitecture (MICRO 57) on 11/03/2024 1pm — 5pm @ AT&T Hotel and Conference Center. Room 106, Austin, TX.

The evolution of computer architecture always starts with designing domain-specific ones and then turning them into general-purpose ones. For example, GPUs were just accelerators for computer graphics two decades ago, but now, GPUs are the most widely used general-purpose vector processors. Recent computer architecture trends again fall back to the wave of designing domain-specific accelerators (DSA). However, research projects have successfully used emerging accelerators for applications beyond their original target domains. Inspired by recent research projects and the story of GPGPUs (General-purpose computing on GPUs), this workshop intends to bring together experts from academia and industry to share their efforts in democratizing domain-specific accelerators. Through the presented work, WDDSA would like to explore the potential to lead the renaissance of general-purpose computing on emerging DSAs. 

While we are interested in work that supports general-purpose computing on recent DSAs, we also encourage submissions in general on DSAs and their infrastructure. This workshop is interested in but is not limited to the following topics.

  1. Novel use cases of an accelerator where applications are outside accelerators’ original application domains
  2. Systems, programming, and software for democratizing domain-specific accelerators.
  3. Architectural support for democratizing domain-specific accelerators.
  4. Performance/power/energy evaluation/analysis of democratizing domain-specific accelerators
  5. Implications to future “democratized” accelerator design.

 This workshop invites three types of presentations.

  1. Track 1: Original research papers. WDDSA welcomes papers on projects working on innovative ideas with preliminary results. WDDSA works together with IEEE Computer Architecture Letters (IEEE CAL) to invite top papers in this track to publish in IEEE CAL.
  2. Track 2: Published research papers with artifacts available. The submission can be based on an already published work (published within 12 months upon the submission deadline). WDDSA provides a platform for these papers to promote their artifacts, allowing the community to use and extend existing projects. The presentation may consider including a live demo.
  3. Track 3: Industry insights. WDDSA also welcomes papers on industry projects, encouraging the industry to have conversations with the academia.

Schedule

Date/TimeTopicSpeaker
11/03/2024 1:00p-1:10pOpening remarksOrganizers
11/03/2024 1:10p-2:00pKeynote I
Innovation Amidst Challenges: Deep Learning Hardware
Abstract:
The semiconductor industry faces a critical juncture as Moore’s Law’s relevance wanes, with the latest technologies like Hopper demonstrating the trade-offs between computational power, cost, and energy consumption. This period of transition challenges the traditional economic and environmental sustainability of semiconductor production. Amid evolving geopolitical and supply chain landscapes, there’s a pressing need for rethinking architectural designs, even leveraging older technologies like the 12nm process for competitive advantage. Amidst this, the length of chip design cycles remains unchanged. Architectural research in AI and deep-learning in particular is entering an unprecedented phase. There is a pressing need for a proliferation of innovative ideas, arguably surpassing the era of out-of-order execution (OOO) in its intensity and necessity. However, it is equally important to ensure that these new ideas are not obscured by outdated concepts. They must be framed, evaluated, and reviewed within the appropriate context by the academic and industrial communities. This talk explores the urgent need for groundbreaking ideas in architecture, addressing a few myths surrounding deep learning hardware and projecting a sustainable, innovative path forward for the industry.		Karu Sankaralingam (UW-Madison)

Karu Sankaralingam is a Professor at UW-Madison, an Entrepreneur and Inventor and leads the Vertical Research Group. His work has been featured in industry forums of Mentor and Synopsys, and has been covered by the New York Times, Wired, and IEEE Spectrum. He has published over 100 research papers, has graduated 10 PhD students, is an inventor on 21 patents, and 9 award papers. He is a Fellow of IEEE. He is a recipient of the Vilas Faculty Early Career Investigator Award in 2018, Wisconsin Innovation Award in 2016, IEEE TCCA Young Computer Architecture Award in 2012, the Emil H Steiger Distinguished Teaching award in 2014, the Letters and Science Philip R. Certain – Gary Sandefur Distinguished Faculty Award in 2013, and the NSF CAREER award in 2009.
11/03/2024 2:10p-2:35pFEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow SwitchingJianming Tong (Georgia Institute of Technology)
Anirudh Itagi (Georgia Institute of Technology)
Prasanth Chatarasi (IBM Research) Tushar Krishna (Georgia Tech)
11/03/2024 2:35p-3:00pIn-Memory Data Processing Optimization with Domain-Specific Accelerators for Scientific ComputingVijayalakshmi Saravanan (University of Texas at Tyler),
Sai Karthik Navuluru,
Khaled Z Ibrahim
11/03/2024 3:00p-3:30pCoffee Break
11/03/2024 3:30p-3:55pAuRORA: Virtualized Accelerator Orchestration for Multi-Tenant WorkloadsSeah Kim
Jerry Zhao
Krste Asanović
Borivoje Nikolić
Yakun Sophia Shao
(University of California, Berkeley, Berkeley)
11/03/2024 4:00p-4:50pTitle AMD’s MI300 APU and GPU ; Domain specific architectures targeted to accelerate HPC and AI

AMD’s journey toward exascale computing has led to the development of advanced Accelerated Processing Units (APUs) and GPUs, exemplified by the AMD Instinct MI300 Series. This series integrates high-performance computing (HPC) and artificial intelligence (AI) capabilities within a single package using AMD’s innovative chiplet architecture, Infinity Cache, and 8-stack HBM3 memory, delivering over 5TBps peak bandwidth. The MI300A and MI300X models leverage advanced heterogeneous integration to enable efficient, domain-specific acceleration for AI and HPC workloads, supporting both CPU-hosted and self-hosted configurations for seamless CPU-GPU synergy in high-density and large model environments. These accelerators reflect AMD’s evolution in packaging and hybrid bonding technologies to drive next-generation AI and exascale performance, Talk will cover the salient features of how MI300A and MI300X accelerates HPC and AI in a domain specific way. 		Vamsi Krishna and Anup Suggula (AMD)

Vamsi Krishna is a Chief Engineer at AMD and an AMD Fellow, where he leads the system deployment of Instinct platforms and accelerators within the DCGPU division. With deep expertise in system debug, validation, and optimization, Vamsi has played a pivotal role in the development and deployment of several generations of Instinct products. His work ensures that AMD’s high-performance computing solutions meet the rigorous demands of modern data centers and research institutions.
As an IEEE Senior Member, Vamsi is recognized for his contributions to the field of computer engineering, particularly in advancing the capabilities of GPU accelerators. His insights and leadership continue to drive innovation in the industry

Anup Suggula is a Chief Engineer and Senior Staff Engineer at AMD, where he spearheads the engineering acceptance of AMD’s cutting-edge Instinct products. Currently, Anup is at the forefront of the system deployment for the MI325x next-generation accelerator from AMD’s DCGPU group. With profound expertise in system validation and a holistic system-first approach to debug, Anup has been instrumental in the development and deployment of multiple generations of AMD Ryzen desktop and laptop processors. His contributions have significantly advanced AMD’s technological prowess and market leadership.

Submission Guidelines

WDDSA has two tracks of paper submissions and each have different submission guidelines. Please read the guidelines carefully.

  • Track 1: Research papers.
    • Papers should be 4 pages in PDF format, following the template of IEEE CAL https://www.computer.org/csdl/journal/ca/write-for-us/15055.
    • Please submit through https://mc.manuscriptcentral.com/cal and check “WDDSA” as the attribute before 9/15/2024
      • Create an account in IEEE CAL’s submission site.
      • After login, click “Author” from the menu bar
      • Fill in your details, and during Step 3: Attributes, please ensure you select “Workshop on Democratizing Domain-Specific Accelerators (WDDSA)”
      • Others are the same as regular CAL submissions
  • Track 2 & 3: Published & industry papers.
    • Please provide a 2-page summary that covers the high-level ideas of the presentation in PDF format. For published work, please also indicate where the paper was published.
    • Please submit through https://wddsa2024.hotcrp.com/

Submission Website

Important Dates

  • Full paper deadline: 9/15/2024
  • Notification of acceptance: 9/30/2024
  • Camera-ready deadline: 10/28/2024

Organizers

  • Yufei Ding (University of California, San Diego)
  • Hari Sadasivan (AMD)
  • Christopher Torng (Stanford University)
  • Po-An Tsai (NVIDIA Research)
  • Hung-Wei Tseng (University of California, Riverside)