EE/CS120A Logic Design (2020, Spring)

Instructor

Hung-Wei Tseng
email: htseng @ ucr.edu
Office Hours: TuF 2p-3p

Teaching Assistant

Yibo Liu
email:
Lab Session: Wed 9a-11:50a
Office Hours: Wed 12p-12p

Luting Yang
e-mail:
Lab Session: Fri 9a-11:50a
Office Hours: M 2p-4p

Course Overview

EE/CS120A introduces you to the exciting world of digital design. Digital circuits not only form the foundation of computers, but make possible many of the advances around us, like cell phones, video games, medical instruments, automotive systems, satellites, music equipment, military equipment, store automation. You name it — if it runs on electricity, it’s probably got digital circuits (known as embedded systems) inside! 120A gets you up to speed on the basics; the follow-up course, 120B, teaches you how to build a computer, and to build complete working embedded computing systems. Finally, you can put your knowledge of digital design to use in EE/CS 168 where you learn the design process of creating Integrated Circuits from a digital design.

Textbook

Digital Design on zyBooks.com

Grading

25% Final
20% Midterm
30% Labs
15% Assignments
2% Class participation
8% reading quizzes
We will have reading quizzes on iLearn!
Additional notes about grades in this course
- Your score will be available on iLearn. Your final grade is the weighted average of these grades.
  We do our best to record grades accurately, but you should double-check.
- Late submission: We do not accept any late submission, including quiz, assignments, projects.
- Errors in grading: If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem. Neither I nor the TAs will discuss regrades without receiving an email from you about it first. For arithmetic errors (adding up points etc.) you do not need to submit anything in writing, but the one week limit still applies.
- For exams: We do not regrade on a single problem. We will re-grade your whole test. The one week regrading window still applies.
- Final grades: The final grading will be based on relative ranking of students in the class instead of absolute scale of grades. If you have a problem with your final grade in the course, send me email and we can set up an appointment to discuss it.

Schedule and Slides

	Topic	Reading	Slides (Preview)	Slides (Release)	Due
3/31/2020	Intro	zyBooks: Chapter #1.1-1.3		Intro
	Lab #1	Lab 1 Lecture		Lab #1 Instructions
4/2/2020	Boolean Algebra & Circuit Gates	zyBooks: Chapter #1.4-1.11	Combinational Logic (Pre-release)	Combinational Logic & Basic Boolean Algebra	Reading Quiz #1
	Lab #2	Lab 2 Lecture		Lab #2 Instructions Lab #2 Modules
4/7/2020	Expressing circuit design in Boolean Equations	zyBooks: Chapter #1.12-1.17 & 2.1-2.5	Verilog (Pre-release)	Combinational Login & Verilog	Reading Quiz #2
4/9/2020	K-Map		KMap (Pre-release)	Simplifying Circuits with Theorems & KMaps	Lab #1
		Lab 3 Lecture		Lab 3 Instructions
4/14/2020	K-Map (2) and Design Examples	zyBooks: Chapter #2.6-2.13, 3.1-3.6		Kmaps (2)	Reading Quiz #3 Assignment #1 (all challenge questions from 1.1 — 2.2)
4/16/2020	Adders		Datapath Components (Pre-release)	Datapath Components (1)	Lab #2
4/21/2020	Muxes, Multipliers, Shifters	zyBooks: Chapter #3.7-3.18		Datapath Components (2) Demo	Reading Quiz #4
4/23/2020	Floating-Point Numbers		Floating Point Numbers (Pre-release)	Floating Point Numbers Demo	Assignment #2
		Lab 4 Lecture		Lab 4 Instructions
4/28/2020	Floating-Point Numbers and Sequential Network — Finite State Machines	zyBooks: Chapter: #4	Sequential Circuits (Pre-release)	Floating Point Numbers (2) & Sequential Circuits	Reading Quiz #5
4/30/2020	Sequential Network — Finite State Machines and Latches			Sequential Circuits	Lab #3
5/5/2020	Midterm Review			Midterm Review	Assignment #3
5/7/2020	Midterm
		Lab 5 Lecture		Lab 5 Instructions
5/12/2020	Sequential Networks — From FSMs to Circuits			From FSMs to Circuits	Lab #4
5/14/2020	Register and Memory	zyBooks: Chapter: #5	Register & Memory (Pre-release)	Register & Memory Demo	Reading Quiz #6
		Lab 6 Lecture		Lab 6 Instructions
5/19/2020	Non-volatile memory and sequential datapath components		Sequential Datapath Components (Pre-release)	Non-volatile memory & sequential datapath components	Assignment #4
5/21/2020	Revisiting datapath components — Shifters, Multipliers, ALU			Pipelining & Multipliers	Lab #5
5/26/2020	High-Level State Machines and RTL Design	zyBooks: Chapter: #6 and Chapter #9.1, #9.5-9.9	HLSM (Pre-release)	Multipliers & HLSM	Reading Quiz #7
5/28/2020	Sequential Network — Timing Constraints & Data Encoding and Application Performance			HLSM & Clock Timing	Assignment #5
6/2/2020	Power consumption and the era of hardware accelerators		Clock, Power, Future (Preview)	Clock, Power, Future
6/4/2020	Final Review			Final Review	Assignment #6 (6/4), Lab #6 (Friday)
6/11/2020	Online @ 11:30 a.m. – 2:30 p.m