CS203: Advanced Computer Architecture (2019 Fall)

Boyce 1471
Lecture: MW 9:30a – 10:50a

Schedule and SlidesAssignments and ProjectLogistics


Hung-Wei Tseng
email: htseng @ ucr.edu
Office Hours: MW 1p-2p @ WCH 406 or by appointment

Teaching Assistant

Shixiong Qi
email: shixiong.qi @ email.ucr.edu
Office hours: TuTh 9:30a-10:30a @ WCH 110 or by appointment

Other important links

Quizzes, Assignments, Gradeing: iLearn
Discussion Forum on Piazza: piazza.com/ucr/fall2019/cs_203_001_19f
Podcasting: https://mediasite.ucr.edu/Mediasite/Catalog/catalogs/cs_203_001_19f

Course Overview

This course will describe the basics of modern processor operation and techniques to optimize your applications. Topics include computer system performance, instruction set architectures, pipelining, branch prediction, memory-hierarchy design, and a brief introduction to multiprocessor architecture issues.

Text books

Required: Patterson & Hennessy, Computer Architecture: A Quantitative Approach, David Patterson & John Hennessy, Morgan Kaufmann, 6th Edition
Required: Other assigned readings throughout the quarter.


  • Homework 15%
    Homeworks will be assigned throughout the course.
  • Class participation 10% (Clicker-based)
    This class uses “peer instruction” and we REQUIRE each of you to download poll everywhere App or navigate/login to their website during the class
  • Reading Quizzes 10%
    We will have reading quizzes on iLearn!
  • Project 10%
    We will have one coding project throughout the quarter. It’s going to be a contest and you will win a prize over it!
  • Midterm 20%
  • Final 35%
    The final will be cumulative.
  • Additional notes about grades in this course
    • Your score will be available on iLearn. Your final grade is the weighted average of these grades.
      We do our best to record grades accurately, but you should double-check.
    • Late submission: We do not accept any late submission, including quiz, assignments, projects.
    • Errors in grading: If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem. Neither I nor the TAs will discuss regrades without receiving an email from you about it first. For arithmetic errors (adding up points etc.) you do not need to submit anything in writing, but the one week limit still applies.
    • For midterm and final: We do not regrade on a single problem. We will re-grade your whole test. The one week regrading window still applies.
    • Final grades: If you have a problem with your final grade in the course, send me email and we can set up an appointment to discuss it.

Schedule and Slides

Topic Reading Slides
Slides (Release) Due Note
09/30/2019 Introduction Chapter 1.1, 1.2, 1.4
Cramming More Components Onto Integrated Circuits, G.E. Moore, Proceedings of the IEEE 86(1):82-85, Jan 1998


10/02/2019 Performance Evaluation (I) Chapter 1.3, 1.4, 1.7, 1.8, 1.9
Performance Evaluation (Preview)Performance(I)
Reading Quiz #1

10/07/2019 Performance Evaluation (II) Andrew Davison. Twelve Ways to Fool the Masses When Giving Performance Results on Parallel Computers. In Humour the Computer, MITP, 1995
M. D. Hill and M. R. Marty. Amdahl’s Law in the Multicore Era. In Computer, vol. 41, no. 7, pp. 33-38, July 2008.

Performance (II)

10/09/2019 Memory Hierachy Appendix B.1-B.4 Memory Hierarchy (Preview)
Performance (III) & Memory Hierarchy (I)
Reading Quiz #2


Move to 10/28/2019 as midterm review

Homework #1 (Due 10/18) Move to 12/02/2019
10/21/2019 Memory Hierachy (II) Chapter 2.1-2.3
Memory Hierarchy (II) Reading Quiz #3
10/23/2019 Memory Hierachy (III)

Memory Hierarchy (III)

Demo (size of structure)

Demo (unaligned access)

10/28/2019 Memory Hierarchy (IV) & Virtual MemoryChapter B.4-B.5 & Chapter 2.4
Memory Hierarchy (IV)

Reading Quiz #4
10/28/2019 Midterm Review

Midterm Review

7pm @ WCH 143
10/30/2019 Virtual Memory & Basic Processor DesignAppendix C.1Virtual Memory (Preview)Virtual Memory

Homework #2
11/04/2019 Midterm

11/06/2019 Basic Processor DesignAppendix C.2, Chapter 3.1 Pipelined Processor (Preview)Basic Pipelined ProcessorReading Quiz #5
11/13/2019 Branch prediction Chapter 3.3
M. Evers, S. J. Patel, R. S. Chappell and Y. N. Patt. An analysis of correlation and predictability: what makes two-level branch predictors work. In proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA’ 98), Barcelona, Spain, 1998, pp. 52-61.
Scott McFarling. Combining Branch Predictors. Technical report WRL-TN-36, 1993.
Branch Prediction (Preview)
Dynamic Branch Prediction

Reading Quiz #6

11/18/2019 OOO Scheduling Chapter 3.4 – 3.6, 3.8
Tomasulo Hangout
Tomasulo Diagram
OOO/Data hazards
Data HazardsReading Quiz #7

11/20/2019 OOO Scheduling K. C. Yeager, “The Mips R10000 superscalar microprocessor,” in IEEE Micro, vol. 16, no. 2, pp. 28-41, April 1996.
R. E. Kessler, “The Alpha 21264 microprocessor,” in IEEE Micro, vol. 19, no. 2, pp. 24-36, March-April 1999.

Dynamic/OoO Instruction SchedulingHomework #3
11/25/2019 OOO Scheduling & SMT
Dynamic/OoO Instruction Scheduling (II)Reading Quiz #8
11/27/2019 CMP Chapter 3.11
Chapter 5.1-5.6
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy. Simultaneous multithreading: maximizing on-chip parallelism. In 22nd Annual International Symposium on Computer Architecture (ISCA ’95), 1995.
(Optional) Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. In the 23rd annual international symposium on Computer architecture (ISCA ’96), 1996

Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. The case for a single-chip multiprocessor. In the 7th international conference on Architectural support for programming languages and operating systems (ASPLOS ’96), 1996.
12/02/2019 Dark Silicon H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam and D. Burger. Dark Silicon and the End of Multicore Scaling. In IEEE Micro, vol. 32, no. 3, pp. 122-134, May-June 2012.
Parallel Programming & Power/Energy


Reading Quiz #9

12/02/2019 Final Review
Final Review Project 7pm @ WCH 143
12/04/2019 TPU, FPGARakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In 36th International Symposium on Microarchitecture, December, 2003.
In-Datacenter Performance Analysis of a Tensor Processing Unit
Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, and Doug Burger. 2016. A cloud-scale acceleration architecture. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49).
Dark Silicon (Preview) Dark Silicon & Future ArchitectureHomework #4

12/09/2019 Final Exam 8a-11a


Assignment #1
– Questions:
Please find the homework questions and complete the homework using the from the following template
– Deliverable
Turn in your solutions through iLearn under the assignment section
– Due
11:59pm 10/18/2019

Assignment #2
– Questions:
Please find the homework questions and complete the homework using the from the following template
– Deliverable
Turn in your solutions through iLearn under the assignment section
– Due
11:59pm 10/30/2019

Assignment #3
– Questions:
Please find the homework questions and complete the homework using the from the following template
– Deliverable
Turn in your solutions through iLearn under the assignment section
– Due
11:59pm 11/20/2019

Assignment #4
– Questions:
Please find the homework questions and complete the homework using the from the following template
– Deliverable
Turn in your solutions through iLearn under the assignment section
– Due
11:59pm 12/04/2019


Please visit the link and clone the code. https://github.com/hungweitseng/CS203-Project/tree/master
– Deliverable
Turn in your solutions through iLearn under the assignment section
– Due
11:59pm 12/02/2019

Integrity Policy

  • Cheating WILL be taken seriously. Doing otherwise is not fair to honest students. It is also not fair to allow the cheater to thing that it is a reasonable alternative in life.
  • Please review the UCR student handbook for more details on Academic Integrity.
  • Anyone copying information or having information copied during a test will receive an F for the class and will not be allowed to drop. They will be reported to their college dean. If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean–I don’t want to be involved. Anyone caught cheating or falsely representing the work of others on the homework will not be allowed to turn in further homework. Your grade will be based exclusively on the tests with a penalty of 25% OR GREATER applied.
  • We photocopy a random sampling of the exams in order to ensure that students do not modify their tests after they have been returned.
  • Online solutions, etc.: A solutions manual exists for this text. Using it, or any solutions you may find on the internet elsewhere IS CHEATING and will be dealt with accordingly. We know what the solution manual solutions look like. Homework is a small fraction of your grade, so cheating on it is unproductive.