Accelerating Fully Homomorphic Encryptions
Our lab focuses on making Fully Homomorphic Encryption (FHE) practical for secure database systems by addressing system-level bottlenecks—such as extreme ciphertext expansion and costly bootstrapping—rather than designing new cryptographic primitives. By employing word-level leveled homomorphic encryption based on the BFV scheme, our architecture uses batch encoding to pack tens of thousands of values into a single ciphertext, minimizing storage overhead while unlocking massive data-level parallelism. Additionally, we incorporate a noise-aware query planner that extends computation depth and executes equality, range, and aggregation operations through purely homomorphic computation, ensuring end-to-end confidentiality without relying on trusted execution environments or transciphering.
Democractizing hardware accelerators
Beyond AI/ML accelerators, modern systems also integrate other types of accelerators for more application domains. Ray Tracing accelerator is one example type of hardware that becomes more popular modern systems to fulfill the demand of gaming and virtual/mixed realities. These accelerators complement the deficiency of AI/ML accelerators in accelerating algorithms with divergent control flows or irregular memory access patterns. Democractizing these accelerators will improve the performance of traditionally hard-to-parallelize problems that currently have to rely on slowly improved CPU architectures.
Accelerating non-AI/ML applications using AI/ML accelerators
The explosive demand on AI/ML workloads drive the emergence of AI/ML accelerators, including commercialized NVIDIA Tensor Cores and Google TPUs. These AI/ML accelerators are essentially matrix processors and are theoretically helpful to any application with matrix operations. This project bridges the missing system/architecture/programming language support in democratizing AI/ML accelerators. As matrix operations are conventionally inefficient, this project also revises the core algorithm in compute kernels to better utilize operators of AI/ML accelerators. With this project, ESCAL envisions ourselves to lead the next trend of a revolution — similar to the one happened on GPUs. You may now try our most recent GPTPU project from the GitHub repo: https://github.com/escalab/GPTPU
Related papers:
- Dongho Ha, Yunan Zhang, Chen-Chien Kao, Woo Woo Ro, Christopher Hughes, Hung-Wei Tseng. M^3XU: Achieving High-Precision and Complex Matrix Multiplication with Low-Precision MXUs. To appear in the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2024.
- Kuan-Chieh Hsu and Hung-Wei Tseng. Simultaneous and Heterogeneous Multithreading. In the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2023. [GitHub]
- Dongho Ha, Woo Won Ro, Hung-Wei Tseng. TensorCV: Accelerating Inference-Adjacent Computation Using Tensor Processors. In 2023 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2023, 2023. [GitHub]
- Yunan Zhang, Po-An Tsai and Hung-Wei Tseng. SIMD^2: A Generalized Matrix Instruction Set for Accelerating Tensor Computation beyond GEMM. In 49th International Symposium on Computer Archi- tecture, ISCA 2022, 2022. [arXiv] [GitHub]
- Yu-Ching Hu, Yuliang Li and Hung-Wei Tseng. TCUDB: Accelerating Database with Tensor Processors. In the 2022 ACM SIGMOD/PODS International Conference on Management of Data, SIGMOD 2022, 2022. [arXiv] [GitHub]
- Kuan-Chieh Hsu and Hung-Wei Tseng. Accelerating Applications using Edge Tensor Processing Units. In The International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2021. [arXiv] [GitHub]
Innovative hardware accelerator architectures
ESCAL also focuses on designing hardware accelerators for important application domains and complement the missing problems that existing accelerators cannot tackle.
- Yunan Zhang, Po-An Tsai and Hung-Wei Tseng. Sparsepipe: Sparse Inter-operator Dataflow Architecture with Cross-Iteration Reuse. In the 57th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2024.
- Dongho Ha, Yunan Zhang, Chen-Chien Kao, Woo Woo Ro, Christopher Hughes, Hung-Wei Tseng. M^3XU: Achieving High-Precision and Complex Matrix Multiplication with Low-Precision MXUs. In International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2024.
