Jinyoung Choi
| Jinyoung Choi is a Ph.D. candidate in the Department of Computer Science and Engineering at the University of California, Riverside. I have the following expertise (from the most experienced): Memory systems for future memory technologies, heterogeneous accelerators (GPU, FPGA, DSA), PCIe, and NVMe. [Resume][ E-mail: jchoi264[at]ucr[dot]edu | ![]() |
Work experiences
- SWE summer intern @Google Cloud Platform, Seattle, WA (Jun 2022 – Sep 2022)
- Research summer intern @AMD Research, Bellevue (remotely), WA (Jun 2020 – Sep 2020)
- Research summer intern @AMD Research, Bellevue, WA (May 2019 – Aug 2019)
- Embedded SWE @Telechip, Inc., Seoul, Korea (Jan 2014 – Jun 2018)
Publications
- Jinyoung Choi, Sergey Blagodurov, and Hung-Wei Tseng. Dancing in the Dark: Profiling for Tiered Memory. 12th Annual Non-Volatile Memories Workshop (NVMW), 2021. [PDF][Slides][Video]
- Jinyoung Choi, Sergey Blagodurov, and Hung-Wei Tseng. Dancing in the Dark: Profiling for Tiered Memory. In 35th IEEE International Parallel & Distributed Processing Symposium, 2021. [PDF][Github]
- Jinyoung Choi, Yu-Ching Hu, Abenezer Wudenhe, and Hung-Wei Tseng. What Can Intelligent SSDs Do for Machine Learning? 10th Annual Non-Volatile Memories Workshop (NVMW), 2019.
Patents
Software
- Tiered-Memory-Profiler: https://github.com/escalab/Tiered-Memory-Profiler
