EE/CS277 (2025 Spring): Data-Centric Computer Architecture
TuTh 9:30a-10:50a
Location: Student Success Center | Room 123
Instructor
Hung-Wei Tseng
email: htseng @ ucr.edu
Office Hours: W 12p-1p or by appointment
Youtube Channel: https://www.youtube.com/profusagi
Course Overview
With the rapid growth of application dataset size and the introduction of hardware accelerators, the non-computational part of an application — the data movement overhead among storage devices, memory units, and computing components becomes the major performance bottleneck. Instead of tweaking the entrenched CPU/compute-centric models in designing systems, architectures, and applications, we need to explore the design from a data-centric perspective.
This class will focus on the underrated architectural components and alternative computing models, including system interconnects in heterogeneous computers, I/O system stacks, emerging non-volatile memory technologies, near-data processing and data flow architectures.
By the end of this course, the students will be able to:
- Obtain a complete overview of interactions among different components in computer systems
- Identify the performance issue of modern heterogeneous computer systems.
- Perform system-level programming on important I/O system modules.
- Propose a data-centric design in addressing performance issues.
- Optimizing the performance of applications on existing heterogeneous computer systems.
This class will be a seminar-style class that requires students to present and discuss the assigned reading materials as well as conducting term projects in groups.
Materials
- Please check the schedule for the reading list!
Grading
- 50% Research Project or Research Survey
This class will encourage students to participate in projects that lead to innovative research outcome. - 50% Class Participation and Discussion
This class will require students to attend and discuss the studied research paper every week. Please submit your paper summary through Gradescope.
Schedule and Slides
| Date | Topic | Reading | Slides(Release) | Note |
|---|---|---|---|---|
| 04/01/2025 | Introduction — The Life of Data in Computer Systems | – Jaeyoung Do, Sudipta Sengupta, and Steven Swanson. 2019. Programmable solid-state storage in future cloud datacenters. Commun. ACM 62, 6 (June 2019), 54–62. | (1) Introduction | |
| 04/03/2025 | The roofline model & the case of hardware accelerators | – Samuel Williams, Andrew Waterman, and David Patterson. 2009. Roofline: an insightful visual performance model for multicore architectures. Commun. ACM 52, 4 (April 2009), 65–76. – N. Jouppi, C. Young, N. Patil and D. Patterson, “Motivation for and Evaluation of the First Tensor Processing Unit,” in IEEE Micro, vol. 38, no. 3, pp. 10-19, May./Jun. 2018, doi: 10.1109/MM.2018.032271057. – (Optional) Norm Jouppi, George Kurian, Sheng Li, Peter Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Clifford Young, Xiang Zhou, Zongwei Zhou, and David A Patterson. 2023. TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ’23). | (2) Roofline Model | |
| 04/08/2025 | Hardware accelerators (I) | – J. Burgess, “RTX on—The NVIDIA Turing GPU,” in IEEE Micro, vol. 40, no. 2, pp. 36-44, 1 March-April 2020 – Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, and Doug Burger. 2016. A cloud-scale acceleration architecture. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). | (3) Hardware Accelerators (1) | |
| 04/10/2025 | Hardware accelerators (2) | (4) Hardware accelerators (2) | ||
| 04/15/2025 | General-purpose computing on hardware accelerators | – H. Esmaeilzadeh, A. Sampson, L. Ceze and D. Burger. Neural Acceleration for General-Purpose Approximate Programs. 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2012) – (Optional) K. Seshadri, B. Akin, J. Laudon, R. Narayanaswami and A. Yazdanbakhsh. An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks. in 2022 IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, USA, 2022 pp. 79-91. | (5) General-purpose computing on accelerators | |
| 04/17/2025 | General-purpose Computing on Hardware Accelerators(2) | – Kuan-Chieh Hsu and Hung-Wei Tseng. Accelerating Applications using Edge Tensor Processing Units. In The International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2021. | (6) GPTPU | |
| 04/22/2025 | General-purpose Computing on Hardware Accelerators (3) | – Yu-Ching Hu, Yuliang Li and Hung-Wei Tseng. TCUDB: Accelerating Database with Tensor Processors. In the 2022 ACM SIGMOD/PODS International Conference on Management of Data, SIGMOD 2022, 2022. – Yuhao Zhu. 2022. RTNN: accelerating neighbor search using hardware ray tracing. In Proceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP ’22) – Jacob, Bruce L. Synchronous DRAM architectures, organizations, and alternative technologies. University of Maryland (2002). | (7) TCUDB/RTNN | |
| 04/24/2025 | Main memory subsystem | (8) Memory technologies | ||
| 04/29/2025 | Main memory subsystem (2) Project Idea Presentations | (9) Memory subsystem (2) | ||
| 05/01/2025 | Project Idea Presentations | |||
| 05/06/2025 | Memory subsystem (3) | – David Patterson, Thomas Anderson, Neal Cardwell, Richard Fromm, Kimberly Keeton, Christoforos Kozyrakis, Randi Thomas, and Katherine Yelick. 1997. A Case for Intelligent RAM. IEEE Micro 17, 2 (March 1997), 34–44. – V. Seshadri et al.. RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization. 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Davis, CA, 2013, pp. 185-197. – (Optional) Mark Oskin, Frederic T. Chong, and Timothy Sherwood. 1998. Active pages: a computation model for intelligent memory. SIGARCH Comput. Archit. News 26, 3 (June 1998), 192–203. | (10) Memory subsystem (3) | |
| 05/08/2025 | In-memory processing (cont.) | – C. Xu, X. Dong, N. P. Jouppi and Y. Xie, “Design implications of memristor-based RRAM cross-point structures,” 2011 Design, Automation & Test in Europe, Grenoble, 2011, pp. 1-6, doi: 10.1109/DATE.2011.5763125. | (11) Near/In- Memory Processing | |
| 05/13/2025 | Peripherals and I/O | – Jisoo Yang, Dave B. Minturn, and Frank Hady. 2012. When poll is better than interrupt. In Proceedings of the 10th USENIX conference on File and Storage Technologies (FAST’12). USENIX Association, USA, 3. | (12) Peripherals and I/O (1) | |
| 05/15/2025 | SSDs | – Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, and Jack K. Wolf. 2009. Characterizing flash memory: anomalies, observations, and applications. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 42) | (13) SSDs | |
| 05/20/2025 | Streamline data exchange | – Yang, Jingpei, et al. “Don’t stack your log on my log.” 2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads (INFLOW 14). 2014. – Shai Bergman, Tanya Brokhman, Tzachi Cohen, and Mark Silberstein. 2017. SPIN: seamless operating system integration of peer-to-peer DMA between SSDs and GPUs. In Proceedings of the 2017 USENIX Conference on Usenix Annual Technical Conference (USENIX ATC ’17). USENIX Association, USA, 167–179 – Jaeyoung Do, Yang-Suk Kee, Jignesh M. Patel, Chanik Park, Kwanghyun Park, and David J. DeWitt. 2013. Query processing on smart SSDs: opportunities and challenges. In Proceedings of the 2013 ACM SIGMOD International Conference on Management of Data (SIGMOD ’13). Association for Computing Machinery, New York, NY, USA, 1221–1230. DOI:https://doi.org/10.1145/2463676.2465295 – (Optional) Matias Bjørling, Jens Axboe, David Nellans, and Philippe Bonnet. 2013. Linux block IO: introducing multi-queue SSD access on multi-core systems. In Proceedings of the 6th International Systems and Storage Conference (SYSTOR ’13). Association for Computing Machinery, New York, NY, USA, Article 22, 1–10. DOI:https://doi.org/10.1145/2485732.2485740 – E. Riedel, C. Faloutsos, G. A. Gibson and D. Nagle, “Active disks for large-scale data processing,” in Computer, vol. 34, no. 6, pp. 68-74, June 2001, doi: 10.1109/2.928624. – (Optional) Jaeyoung Do, Sudipta Sengupta, and Steven Swanson. 2019. Programmable solid-state storage in future cloud datacenters. Commun. ACM 62, 6 (June 2019), 54–62. | (14) Streamline Data Exchange | |
| 05/22/2025 | SmartSSDs | – Animesh Trivedi, Patrick Stuedi, Jonas Pfefferle, Adrian Schuepbach, Bernard Metzler. Albis: High-Performance File Format for Big Data Systems. 2018 USENIX Annual Technical Conference (USENIX ATC 18) – Hung-Wei Tseng, Qianchen Zhao, Yuxiao Zhou, Mark Gahagan, and Steven Swanson. 2016. Morpheus: creating application objects efficiently for heterogeneous computing. SIGARCH Comput. Archit. News 44, 3 (June 2016), 53–65. DOI:https://doi.org/10.1145/3007787.3001143 – (Optional) Rajeev Balasubramonian Jichuan Chang Troy Manning Jaime H. Moreno Richard Murphy Ravi Nair Steven Swanson. Near-Data Processing: Insights from a MICRO-46 Workshop. IEEE Micro (Special Issue on Big Data), vol. 34 (2014), pp. 36-43 | (15) SmartSSD | |
| 05/27/2025 | Data formats matter | – Yang, Jingpei, et al. “Don’t stack your log on my log.” 2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads ({INFLOW} 14). 2014. – Yanqin Jin, Hung-Wei Tseng, Yannis Papakonstantinou, Steven Swanson, KAML: A Flexible, High-Performance Key-Value SSD. The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA 2017) – (Optional) Yu-Ching Hu, Murtuza Taher Lokhandwala, Te I., and Hung-Wei Tseng. 2019. Dynamic Multi-Resolution Data Storage. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ’52). Association for Computing Machinery, New York, NY, USA, 196–210. DOI:https://doi.org/10.1145/3352460.3358282 | (16) Data formats matter | |
| 05/29/2025 | System design & Final Presentations | – J. H. Saltzer, D. P. Reed, and D. D. Clark. 1984. End-to-end arguments in system design. ACM Trans. Comput. Syst. 2, 4 (Nov. 1984), 277–288. – B. W. Lampson. Hints for computer system design. The Ninth ACM Symposium on Operating System Principles (SOSP), October 1983, pp. 33-48. | (17) System Design | |
| 06/03/2025 | Final Presentations | |||
| 06/05/2025 | No lecture |
Other References
– Dongping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Lifan Xu, and Michael Ignatowski. 2014. TOP-PIM: throughput-oriented programmable processing in memory. In Proceedings of the 23rd international symposium on High-performance parallel and distributed computing (HPDC ’14). Association for Computing Machinery, New York, NY, USA, 85–98. DOI:https://doi.org/10.1145/2600212.2600213
– Hoang Anh Du Nguyen, Jintao Yu, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui, and Francky Catthoor. 2020. A Classification of Memory-Centric Computing. J. Emerg. Technol. Comput. Syst. 16, 2, Article 13 (April 2020), 26 pages. DOI:https://doi.org/10.1145/3365837
– S. Aga, S. Jeloka, A. Subramaniyan, S. Narayanasamy, D. Blaauw and R. Das, “Compute Caches,” 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, 2017, pp. 481-492, doi: 10.1109/HPCA.2017.21.
– Ke Wang, Kevin Angstadt, Chunkun Bo, Nathan Brunelle, Elaheh Sadredini, Tommy Tracy, Jack Wadden, Mircea Stan, and Kevin Skadron. 2016. An overview of micron’s automata processor. In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES ’16). Association for Computing Machinery, New York, NY, USA, Article 14, 1–3. DOI:https://doi.org/10.1145/2968456.2976763
– Youngeun Kwon, Yunjae Lee, and Minsoo Rhu. 2019. TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ’52). Association for Computing Machinery, New York, NY, USA, 740–753. DOI:https://doi.org/10.1145/3352460.3358284
– Boncheol Gu, Andre S. Yoon, Duck-Ho Bae, Insoon Jo, Jinyoung Lee, Jonghyun Yoon, Jeong-Uk Kang, Moonsang Kwon, Chanho Yoon, Sangyeun Cho, Jaeheon Jeong, and Duckhyun Chang. 2016. Biscuit: a framework for near-data processing of big data workloads. SIGARCH Comput. Archit. News 44, 3 (June 2016), 153–165. DOI:https://doi.org/10.1145/3007787.3001154
– Matias Bjørling, Jens Axboe, David Nellans, and Philippe Bonnet. 2013. Linux block IO: introducing multi-queue SSD access on multi-core systems. In Proceedings of the 6th International Systems and Storage Conference (SYSTOR ’13). Association for Computing Machinery, New York, NY, USA, Article 22, 1–10. DOI:https://doi.org/10.1145/2485732.2485740
– Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh, and Vijay Balakrishnan. 2015. Performance analysis of NVMe SSDs and their implication on real world databases. In Proceedings of the 8th ACM International Systems and Storage Conference (SYSTOR ’15). Association for Computing Machinery, New York, NY, USA, Article 6, 1–11. DOI:https://doi.org/10.1145/2757667.2757684
– T. Coughlin, “A Solid-State Future [The Art of Storage],” in IEEE Consumer Electronics Magazine, vol. 7, no. 1, pp. 113-116, Jan. 2018, doi: 10.1109/MCE.2017.2755339.
– Seshadri, Sudharsan, et al. “Willow: A User-Programmable {SSD}.” 11th {USENIX} Symposium on Operating Systems Design and Implementation ({OSDI} 14). 2014
– Yanqin Jin, Hung-Wei Tseng, Yannis Papakonstantinou, Steven Swanson, KAML: A Flexible, High-Performance Key-Value SSD. The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA 2017).
– Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi Iyer, Dennis Sylvester, David Blaauw, and Reetuparna Das. 2018. Neural cache: bit-serial in-cache acceleration of deep neural networks. In Proceedings of the 45th Annual International Symposium on Computer Architecture (ISCA ’18).
– W. A. Simon, Y. M. Qureshi, M. Rios, A. Levisse, M. Zapater and D. Atienza, “BLADE: An in-Cache Computing Architecture for Edge Devices,” in IEEE Transactions on Computers, vol. 69, no. 9, pp. 1349-1363, 1 Sept. 2020, doi: 10.1109/TC.2020.2972528.
– K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally and M. Horowitz, “Smart Memories: a modular reconfigurable architecture,” Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), Vancouver, BC, Canada, 2000, pp. 161-171, doi: 10.1109/ISCA.2000.854387.