CS203: Advanced Computer Architecture (2025 Fall)

Lecture: TuTh 11a – 12:20p

Where: WCH 143

Schedule and SlidesAssignmentsLogisticsMy Grade

Instructor

Hung-Wei Tseng
email: cs203 @ escalab.org
Office Hours: TuW 1p-2p @ WCH 406

Teaching Assistant

Hongrui Zhang
email: cs203 @ escalab.org
Office Hours: W 4p-5p @ Zoom; Th 2p-4p @ WCH 110

Other important links

Course overview

This course will describe the basics of modern processor operation and techniques to optimize your applications. Topics include computer system performance, instruction set architectures, pipelining, branch prediction, memory-hierarchy design, and a brief introduction to multiprocessor architecture issues.

Text books

Required: Patterson & Hennessy, Computer Architecture: A Quantitative Approach, David Patterson & John Hennessy, Morgan Kaufmann, 6th Edition and assigned research papers.
Required: Other assigned readings throughout the quarter.

Many research papers will require campus network to download. For instructions of connecting to UCR VPN and download research papers, please visit https://library.ucr.edu/using-the-library/technology-equipment/connect-from-off-campus

Grading and policies

  • Course Agreement
    • Please review and complete the course agreement before you start working on the class. Any effort made prior to the course agreement does not count toward your final grade.
  • We don’t encourage/accommodate enrollment later than 9/15/2025
    • As the school allocate TA/tutor resources based on the initial enrollment. Late enrollment will hurt our education quality and we strongly encourage you to enroll in this class before 9/15/2025
    • As we discourage late enrollment, if you miss any deadline or having issues accessing the Gradescope/datahub platforms due to your late enrollment, we will not accommodate that and you have to bear the consequences of missing those deadline.
  • Assignments 30%
    • Assignments will be assigned throughout the course. We will drop your lowest one.
    • Our assignments will be based on Jupyterhub/Jupyter notebooks and programming — everyone is supposed to have a unique turnin. There is no group submission or collaboration allowed.
    • There is no regrading on assignments except for obvious grading errors. Please make sure your answers are clearly comprehensible to our grading staffs and follow the guideline of answering assignment questions.
    • Peer instruction
      • This class uses “peer instruction” as our teaching method
      • To encourage your participation in peer instructions, we count your participation in peer instructions throughout the quarter as one assignment. In other words, if you opt out from peer instructions, this one will become the one that is dropped from your assignments.
      • To participate in peer instructions, we require each of you to download poll everywhere App or navigate/login to their website during the class if you would like to earn credits from participating in peer instructions.
      • You must login with UCRNetID@ucr.edu. If you didn’t do it right, you won’t get credits.
      • You need to answer 50% of the poll questions to receive full credits on peer instructions.
  • Reading Quizzes 20%
    • We will have reading quizzes on GradeScope
    • Only one shot, but time unlimited. We will drop your lowest two quiz grades.
  • Midterm 20%
  • Final 30%
  • Additional notes about grades/assignments in this course
    • Your score will be available on https://www.escalab.org/my_grades/. Your final grade is the weighted average of these grades.
      We do our best to record grades accurately, but you should double-check.
    • Deadlines.
      • All deadlines are hard deadlines. You should not expect any extension of the deadline.
      • It is your responsibility to keep up with the schedule.
      • We won’t grant any exception especially for late enrollment. You should have enrolled and prioritized CS203 over other courses if you’re really interested in this class.
      • If you have medical emergency that prevents you from finishing on time, you have to provide the proof before asking for extensions.
    • Late submission: We do not accept any late submission, including quiz and assignments unless you obtain a proof from Student Disability Resource Center and give us a notice at least 24 hours before the submission due date.
      • Errors in grading: If you feel there has been an error in how an examine was graded, you have one week from when the examine is return to bring it to our attention. For items with submissions through gradescope, please create a request through gradescope.

Schedule and Slides


TopicReadings (Required)Preview SlidesSlides & DemoDue DatesRelease/Notes
9/25/2025Introduction

How to start CS203 assignments		– G.E. Moore. Cramming More Components Onto Integrated Circuits. Electronics, pp. 114–117, April 19, 1965.

– P&H (Textbook): Chapter 1.1-1.6

– John L. Hennessy and David A. Patterson. A new golden age for computer architecture. Communications of the ACM, Volume 62, Issue 2, 2019		(1) Why shouldn’t you be “I don’t care”

Demo: algorithm complexity is not everything		Programming Assignment 1 Released

Please watch this video before you start working on assignments
9/30/2025Performance Evaluation (I)– x86-64 Machine-Level Programming

– P&H (Textbook): Chapter 1.8		Performance (Preview)(2) Performance (1): What does perfect mean?

Demos:
1. Programming Languages & Performance

2. Programmers & CPI — matrix addition

3. Programmers & CPI — sorting

4. Programmers & CT

5. Compilers		Reading Quiz #1 (covers materials of 9/30 and 10/02) due before lecture
Course agreement due before lecture		Assignment 1 Released
10/2/2025Performance Evaluation (II)– P&H (Textbook): Chapter 1.9

– M. D. Hill and M. R. Marty. Amdahl’s Law in the Multicore Era. in Computer, vol. 41, no. 7, pp. 33-38, July 2008.		(3) Performance (2): What does “better” mean?

Demo:
1. Profiling Tools to Find the Most Common Case

2. Optimization is a moving target		Programming Assignment #1 due
10/7/2025Performance Evaluation (III)– Andrew Davison. Twelve Ways to Fool the Masses When Giving Performance Results on Parallel Computers. In Humour the Computer , MIT Press, 1995, pp.38-42.(4) Performance (3): Don’t be a great pretender

Demo:
1. Is FLOPS meaningful or harmful?
2. Throughput v.s. Latency		Reading Quiz #2: Covering the required reading for 10/7 and 10/9
10/9/2025Memory Hierarchy (1): The Basics– P&H (Textbook): Appendix B.1-B.3Memory (Preview)(5) Memory (1): Inside out of our memory hierarchy

Demo:
1. Locality
2. Cache configurations		Assignment 1 dueAssignment 2 and
Programming Assignment 2
Release
10/13/2025–10/17/2025Practice ExaminePlease schedule your practice examine through Testing Center to get familiar with environment
10/14/2025Memory Hierarchy (2)– P&H (Textbook): Appendix B.1-B.3, 2.3
(6) Memory (2): The ABCS of our caches

Demo:
1. Cache configurations — C=ABS
2. Cache configurations (2-way) — C=ABS		Reading Quiz #3 on
– P&H (Textbook): Appendix B.1-B.3, 2.3
– Norman P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. ISCA 1990
10/16/2025Memory Hierarchy (3): Optimizing Cache Performance– P&H (Textbook): Chapter 2.3

– Norman P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. ISCA 1990		(7) Memory (3): Cache misses and their remedies

Demo:
1. Tegra Orin
2. Core i7 14700K		Assignment 3 release
10/21/2025Memory Hierarchy (4): Programmer’s optimizations
(8) Memory (4): cache misses and their remedies

Demo:
1. Data layout/structures
2. Loop Optimizations		Reading Quiz #4 on
– P&H (Textbook): Chapter B.4 & B.5, 2.4

– Thomas W. Barr, Alan L. Cox, and Scott Rixner. 2010. Translation caching: skip, don’t walk (the page table). ISCA 2010
10/23/2025Memory Hierarchy (5): Case Study – Matrix Multiplications
(9) Memory (5): Matrix Multiplications

Demo:
1. Matrix multiplications does not scale with computational complexity
2. Matrix tiling to reduce capacity misses and conflict misses
3. Using register variables to reduce memory accesses
4. Matrix transpose to further improve spatial locality
5. Rectangular matrix tiles to fill the cache better
6. Prefetching to remove compulsory misses		Assignment 2 due
10/27/2025–10/31/2025MidtermPlease schedule your midterm through Testing Center

If you take the midterm on/before 10/28, we cover the material up to 10/23. If you take the midterm on/after 10/29, we cover the material up to 10/28.
10/28/2025Virtual Memory– P&H (Textbook): Chapter B.4 & B.5, 2.4

– Thomas W. Barr, Alan L. Cox, and Scott Rixner. 2010. Translation caching: skip, don’t walk (the page table). ISCA 2010		Virtual Memory (Preview)(10) Virtual Memory

Demo:
Virtual memory in our systems		Reading Quiz #5 on
– P&H (Textbook): Chapter 3.3
– P&H (Textbook): Appendix C.1 – C.4
10/30/2025Basic Processor Design & Branch Prediction– P&H (Textbook): Chapter 3.3
– P&H (Textbook): Appendix C.1 – C.4
Basic Processor Design (Preview)(11) Basic Processor Design

Demo: XOR vs. temp		Assignment 3 due
11/4/2024Advanced Branch Prediction– M. Evers, S. J. Patel, R. S. Chappell and Y. N. Patt, “An analysis of correlation and predictability: what makes two-level branch predictors work,” Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235), Barcelona, Spain, 1998, pp. 52-61.

– S. McFarling, “Combining branch predictors,” Technical Report m-36, Digital Western Research Laboratory, June 1993.

– R. E. Kessler, E. J. McLellan and D. A. Webb, “The Alpha 21264 microprocessor architecture,” Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273), Austin, TX, USA, 1998, pp. 90-95, doi: 10.1109/ICCD.1998.727028.

– Jiménez, Daniel A., and Calvin Lin. “Dynamic branch prediction with perceptrons.” Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture. IEEE, 2001.

– André Seznec and P. Michaud. A case for (partially) TAgged GEometric history length branch prediction. Journal of Instruction Level Parallelism. June 2006.		(12) Dynamic Branch Prediction (1): I guess I just feel like

Demo: the overhead of branch		Reading Quiz #6 on
– M. Evers, S. J. Patel, R. S. Chappell and Y. N. Patt, “An analysis of correlation and predictability: what makes two-level branch predictors work,” Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235), Barcelona, Spain, 1998, pp. 52-61.

-S. McFarling, “Combining branch predictors,” Technical Report m-36, Digital Western Research Laboratory, June 1993.

– R. E. Kessler, E. J. McLellan and D. A. Webb, “The Alpha 21264 microprocessor architecture,” Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273), Austin, TX, USA, 1998, pp. 90-95, doi: 10.1109/ICCD.1998.727028.

– Jiménez, Daniel A., and Calvin Lin. “Dynamic branch prediction with perceptrons.” Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture. IEEE, 2001.

– André Seznec and P. Michaud. A case for (partially) TAgged GEometric history length branch prediction. Journal of Instruction Level Parallelism. June 2006.
– P&H (Textbook): Chapter 3.4 

Assignment 4 release
11/6/2025Data Hazards & OoO– P&H (Textbook): Chapter 3.4  (13) Modern Processor Design (3): Right Here Waiting

Demo: the effect of pipelining		Programming Assignment #2
due
11/11/2025Veterans Day — No lecture
11/13/2025OOO Scheduling– K. C. Yeager, “The MIPS R10000 superscalar microprocessor,” in IEEE Micro, vol. 16, no. 2, pp. 28-41, April 1996.

– E. Rotem et al.. Intel Alder Lake CPU Architectures. in IEEE Micro, vol. 42, no. 3, pp. 13-19, 2022.

– (Optional) A. Gonzalez, J. Gonzalez and M. Valero, “Virtual-physical registers,” Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, NV, USA, 1998, pp. 175-184, doi: 10.1109/HPCA.1998.650557.		Data hazards and OoO scheduling (preview)(14) OoO: Try everythingReading quiz #7 due

Programming Assignment #3
Released
11/18/2025Programming on modern SuperScalar/OoO processors
(15) Programming on Modern Processors: The Single Thread Version

Demo:
1. Linked List vs Array
2. popcounts
Reading Quiz #8 Due
11/20/2025Parallel Architectures & Parallel Programming– P&H (Textbook): Chapter 3.11

– Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm, ISCA ’96: Proceedings of the 23rd annual international symposium on Computer architecture, New York, NY, USA, 1996, pages 191-202.

– Chapter 5.1 – 5.3, 5.5 & 5.6

– The case for a single-chip multiprocessor, Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang, SIGPLAN Not. 31(9):2-11, 1996.		Parallel Architecture (Preview)(16) Parallel Architectures (1)

Demo:
1. SMT
2. SMT vs CMP		Assignment 4 due
11/25/2025Parallel Architectures & Parallel ProgrammingLuiz André Barroso, Jeffrey Dean, and Urs Hölzle. 2003. Web Search for a Planet: The Google Cluster Architecture. IEEE Micro 23, 2 (March 2003), 22–28.

– P&H (Textbook): Chapter 1.7

– Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In 36th International Symposium on Microarchitecture, December, 2003.
(17) Programming on modern processor: the multithreaded version

Demo:
1. Cache coherency
2. Cache consistency
Reading Quiz 9 Due

Assignment  #5 Released

12/2/2024Dark Silicon– H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam and D. Burger. Dark Silicon and the End of Multicore Scaling. In IEEE Micro, vol. 32, no. 3, pp. 122-134, May-June 2012.

– Amin Vahdat, Xiaoyu Ma, David Patterson. New Computer Evaluation Metrics for a Changing World. Communications of the ACM. 2024		(18) The Dark Silicon Era

Demo:
1. Power and energy
2. big.Little
Reading Quiz 10
12/4/2025A new golden age of computer architecture– William J. Dally, Yatish Turakhia, and Song Han. Domain-specific hardware accelerators. Communications of the ACM 63, 7, 2020.

– Norman P. Jouppi, Cliff Young, et. al.. In-Datacenter Performance Analysis of a Tensor Processing Unit. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA 2017).

– John L. Hennessy and David A. Patterson. A new golden age for computer architecture. Communications of the ACM, Volume 62, Issue 2, 2019

– (Optional) Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman Jouppi, and David Patterson. The Design Process for Google’s Training Chips: TPUv2 and TPUv3. In IEEE Micro, vol. 41, no. 2, pp. 56-63, 1 March-April 2021, doi: 10.1109/MM.2021.3058217
(19) The New Golden Age of Computer ArchitectureAssignment  #5 &
Programming Assignment #3 Due
12/8/2025-12/11/2025Final ExamPlease schedule your final exam through Testing Center

For CS203 students from a prior quarter taking the make-up CEP questions, please fill the form
https://forms.gle/Prem6vmA3wMTmRveA

Assignments

You are strongly encouraged to watch this video before you start your first assignment.

Programming Assignment #1 (Due 10/2/2025)
Assignment #1 (Due 10/9/2025)
Assignment #2 (Due 10/23/2025)
Assignment #3 (Due 10/30/2025)
Programming Assignment #2 (Due 11/6/2025)
Assignment #4 (Due 11/20/2025)
Assignment #5 (Due 12/04/2025)
Programming Assignment #3 (Due 12/04/2025)

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Please find your current grade in the following iframe or log in through https://www.escalab.org/my_grades/ first. The grade is updated periodically, not always up-to-date.

Other Policies

Integrity Policy

  • Cheating WILL be taken seriously. Doing otherwise is not fair to honest students. It is also not fair to allow the cheater to thing that it is a reasonable alternative in life.
  • Please review the UCR student handbook for more details on Academic Integrity.
  • Anyone copying information or having information copied during a test will receive an F for the class and will not be allowed to drop. They will be reported to their college dean. If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean–I don’t want to be involved. Anyone caught cheating or falsely representing the work of others on the homework will not be allowed to turn in further homework. Your grade will be based exclusively on the tests with a penalty of 25% OR GREATER applied.
  • We photocopy a random sampling of the exams in order to ensure that students do not modify their tests after they have been returned.
  • Online solutions, etc.: A solutions manual exists for this text. Using it, or any solutions you may find on the internet elsewhere IS CHEATING and will be dealt with accordingly. We know what the solution manual solutions look like. Homework is a small fraction of your grade, so cheating on it is unproductive.

Public Health Regulation

  • If you have any symptom of COVID-19 or seasonal flu, please stay at home.