CS203: Advanced Computer Architecture (2024 Spring)
Lecture: TuTh 9:30a – 10:50a
Where: SOM EDUCATION I | Room G650
Instructor
Hung-Wei Tseng
email: cs203 @ escalab.org
Office Hours: W 2p-4p @ WCH 406
Teaching Assistant
Nurlan Nazaraliyev
email: cs203 @ escalab.org
Office Hours: M 2p-4p @ WCH 110
Other important links
- Assignment & Reading quizzes submission through Gradescope
- Discussion Forum on Piazza
- Lecture recordings: Youtube Channel
- Calendar: Google Calendar
Course Overview
This course will describe the basics of modern processor operation and techniques to optimize your applications. Topics include computer system performance, instruction set architectures, pipelining, branch prediction, memory-hierarchy design, and a brief introduction to multiprocessor architecture issues.
Text books
Required: Patterson & Hennessy, Computer Architecture: A Quantitative Approach, David Patterson & John Hennessy, Morgan Kaufmann, 6th Edition and assigned research papers.
Required: Other assigned readings throughout the quarter.
Many research papers will require campus network to download. For instructions of connecting to UCR VPN and download research papers, please visit https://library.ucr.edu/using-the-library/technology-equipment/connect-from-off-campus
Grading
- Course Agreement
- Please review and complete the course agreement before you start working on the class. Any effort made prior to the course agreement does not count toward your final grade.
- Assignments 25%
- Assignments will be assigned throughout the course. We will drop your lowest one.
- Our assignments will be based on Jupyterhub/Jupyter notebooks and programming — everyone is supposed to have a unique turnin. There is no group submission or collaboration allowed.
- There is no regrading on assignments except for obvious grading errors. Please make sure your answers are clearly comprehensible to our grading staffs and follow the guideline of answering assignment questions.
- Peer instruction
- This class uses “peer instruction” as our teaching method
- To encourage your participation in peer instructions, we count your participation in peer instructions throughout the quarter as one assignment. In other words, if you opt out from peer instructions, this one will become the one that is dropped from your assignments.
- To participate in peer instructions, we require each of you to download poll everywhere App or navigate/login to their website during the class if you would like to earn credits from participating in peer instructions.
- You must login with UCRNetID@ucr.edu. If you didn’t do it right, you won’t get credits.
- You need to answer 50% of the poll questions to receive full credits on peer instructions.
- Reading Quizzes 15%
- We will have reading quizzes on GradeScope
- Only one shot, but time unlimited. We will drop your lowest two quiz grades as well.
- Midterm 25%
- Final 35%
The final will be cumulative. - Additional notes about grades in this course
- Your score will be available on gradescope. Your final grade is the weighted average of these grades.
We do our best to record grades accurately, but you should double-check. - Late submission: We do not accept any late submission, including quiz and assignments unless you obtain a proof from Student Disability Resource Center and give us a notice 24 hours before the submission due date.
- Errors in grading: If you feel there has been an error in how an examine was graded, you have one week from when the examine is return to bring it to our attention. For items with submissions through gradescope, please create a request through gradescope.
- For midterm and final: We do not regrade on a single problem. We will re-grade your whole test.
- Final grades: If you have a problem with your final grade in the course, send me email and we can set up an appointment to discuss it.
- Your score will be available on gradescope. Your final grade is the weighted average of these grades.
Schedule and Slides
| Date | Topic | Readings (Required) | Preview Slides | Slides & Demo | Reading Quiz Due | Assignment Due |
|---|---|---|---|---|---|---|
| 04/02/2024 | Introduction | – G.E. Moore. Cramming More Components Onto Integrated Circuits. Electronics, pp. 114–117, April 19, 1965. – Chapter 1.1-1.6 – John L. Hennessy and David A. Patterson. 2019. A new golden age for computer architecture. Commun. ACM 62, 2 | (1) Why CS203? Demo: Why do you need CS203? | Course Agreement Due 9am 04/02/2024 — You must complete this before taking the course Assignment #1 released. Tips to start CS203 assignments | ||
| 04/04/2024 | Performance Evaluation (I) | – Chapter 1.3 & 1.8-1.9 – x86-64 Machine-Level Programming | Performance (Preview) | (2) Performance (1): What matters? Demo: What can programmers affect? | Reading Quiz #1 | Assignment #2 Released |
| 04/09/2024 | Performance Evaluation (II) | – M. D. Hill and M. R. Marty. Amdahl’s Law in the Multicore Era. in Computer, vol. 41, no. 7, pp. 33-38, July 2008. – V. Sze, Y. -H. Chen, T. J. Yang and J. S. Emer. How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful. In IEEE Solid-State Circuits Magazine, vol. 12, no. 3, pp. 28-41, Summer 2020. | (3) Performance(2): What’s better? Demo: Programming languages/compilers | |||
| 04/11/2024 | Performance Evaluation (III) | (Optional) Andrew Davison, Twelve Ways to Fool the Masses When Giving Performance Results on Parallel Computers. in Humour the Computer , MITP, 1995, pp. | (4) Performance (3): Do the right thing Demo: Amdahl’s Law | Assignment #1 Due 11:59pm 04/11/2024 | ||
| 04/16/2024 | Memory Hierarchy (1): The Basics | – Appendix B.1-B.3 | Memory Hierarchy (Preview) | (5) Memories (1): Inside out of your memories hierarchy Demo: Right Metrics | Reading Quiz #2 | |
| 04/18/2024 | Memory Hierarchy (2) | – Appendix B.1-B.3 – Chapter 2.3 | (6) Memories (2): The A, B, Cs of Your Cache Demo: Localities and cache parameters | Assignment #2 Due 11:59pm 04/18/2024 | ||
| 04/23/2024 | Memory Hierarchy (3) | – Chapter 2.3 | (7) Memories (3): Cache misses and where to find them Demo: Cache misses on Jetson Nano and Intel Core i7 13700 | Reading Quiz #3 | Assignment #3 Released | |
| 04/25/2024 | Memory Hierarchy (4): Optimizing Cache Performance | – Norman P. Jouppi. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. SIGARCH Comput. Archit. News 18, 2SI (June 1990), 364–373. | (8) Memories (4): Causes of cache misses and hardware optimizations Demo: prefetch | |||
| 04/30/2024 | Memory Hierarchy (5): Optimizing Cache Performance — the software approach | (9) Memories (5): Software Optimizations Demo: software optimizations | Reading Quiz #4 | |||
| 05/02/2024 | Virtual Memory (II) | – Chapter B.4 & B.5, 2.4 – Thomas W. Barr, Alan L. Cox, and Scott Rixner. 2010. Translation caching: skip, don’t walk (the page table). In Proceedings of the 37th annual international symposium on Computer architecture (ISCA ’10) – Emily Blem, Jaikrishnan Menon, and Karthikeyan Sankaralingam. 2013. Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. In Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (HPCA ’13). https://minds.wisconsin.edu/handle/1793/64923 | Virtual Memory (Preview) | (10) Virtual Memory: Illusion Demo: Virtual memory | Assignment #3 Due 11:59pm 05/02/2024 | |
| 05/07/2024 | Midterm | Midterm Review | ||||
| 05/09/2024 | Basic Processor Design & Pipeline Hazards | – Chapter 3.3 – Appendix C.1 – C.4 | Basic Processor Design & Branch Prediction (Preview) | (11) Basic Processor Design & Structural Hazard Demo: useless C/C++ programming tricks | Assignment 4 Released | |
| 05/14/2024 | Branch Prediction | – M. Evers, S. J. Patel, R. S. Chappell and Y. N. Patt, “An analysis of correlation and predictability: what makes two-level branch predictors work,” Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235), Barcelona, Spain, 1998, pp. 52-61. | (12) Branch Prediction: What’s next? Demo: branch penalty | Reading Quiz #5 | ||
| 05/16/2024 | Branch Prediction (cont.) | – James E. Smith. Retrospective: a study of branch prediction strategies. ISCA ’98: 25 years of the international symposia on Computer architecture (selected papers), New York, NY, USA, 1998, pages 22-23 – Jiménez, Daniel A., and Calvin Lin. “Dynamic branch prediction with perceptrons.” Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture. IEEE, 2001. – André Seznec and P. Michaud. A case for (partially) TAgged GEometric history length branch prediction. Journal of Instruction Level Parallelism. June 2006. – Chapter 3.4 | (13) Branch Prediction (2): Come to your sense! Demo: popcount! | |||
| 05/21/2024 | Data hazards & data forwarding | – (Optional) D. Suggs, M. Subramony and D. Bouvier, “The AMD “Zen 2” Processor,” in IEEE Micro, vol. 40, no. 2, pp. 45-52, 1 March-April 2020, doi: 10.1109/MM.2020.2974217. | Data Hazard/Dynamic Instruction Scheduling (preview) | (14) Data Hazards Demo: more on popcount! | Reading Quiz #6 | |
| 05/23/2024 | OOO Scheduling | – K. C. Yeager. The MIPS R10000 superscalar microprocessor. in IEEE Micro, vol. 16, no. 2, pp. 28-41, April 1996. | (15) OoO execution | Assignment #4 Due 11:59pm 05/23/2024 | ||
| 05/28/2024 | Programming Modern Processors (2) & SMT | – E. Rotem et al.. Intel Alder Lake CPU Architectures. in IEEE Micro, vol. 42, no. 3, pp. 13-19, 1 May-June 2022 – Chapter 3.11 – Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm, ISCA ’96: Proceedings of the 23rd annual international symposium on Computer architecture, New York, NY, USA, 1996, pages 191-202. – Chapter 5.1 – 5.3, 5.5 & 5.6 – The case for a single-chip multiprocessor, Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang, SIGPLAN Not. 31(9):2-11, 1996. | (16) Super Scalar and SMT Demo: ILP in linked list and array | Reading Quiz #7 | Assignment #5 Released | |
| 05/30/2024 | Chip Multiprocessors & Modern Processors | – E. Rotem et al.. Intel Alder Lake CPU Architectures. in IEEE Micro, vol. 42, no. 3, pp. 13-19, 1 May-June 2022 – Luiz André Barroso, Jeffrey Dean, and Urs Hölzle. 2003. Web Search for a Planet: The Google Cluster Architecture. IEEE Micro 23, 2 (March 2003), 22–28. – (Optional) M. Evers, L. Barnes and M. Clark, “The AMD Next-Generation “Zen 3” Core,” in IEEE Micro, vol. 42, no. 3, pp. 7-12, 1 May-June 2022, doi: 10.1109/MM.2022.3152788. https://ieeexplore.ieee.org/document/9718180 | Parallel Architectures (Preview) | (17) Parallel Architecture/Programming Demo: Cache coherency | ||
| 06/04/2024 | Parallel architectures & Dark Silicon | – Chapter 1.7 – H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam and D. Burger. Dark Silicon and the End of Multicore Scaling. In IEEE Micro, vol. 32, no. 3, pp. 122-134, May-June 2012. – Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In 36th International Symposium on Microarchitecture, December, 2003. | (18) Parallel Programming and Dark Silicon Problem Demo: Cache coherency | Reading Quiz #8 | ||
| 06/06/2024 | TPU, FPGA | – Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, and Doug Burger. 2016. A cloud-scale acceleration architecture. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). – Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, and Doe Hyun Yoon. 2017. In-Datacenter Performance Analysis of a Tensor Processing Unit. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA ’17). Association for Computing Machinery, New York, NY, USA, 1–12. DOI:https://doi.org/10.1145/3079856.3080246 – John L. Hennessy and David A. Patterson. 2019. A new golden age for computer architecture. Commun. ACM 62, 2 | (19) The new golden age of computer architects! Demo: consistency Demo: Power Demo: big.Little | Assignment #5 Due 11:59pm 06/09/2024 | ||
06/14/2024 8am — 11am @ BOYHL 1471 | Final Exam | (If you’re a student from a prior quarter and would like to take a makeup comprehensive exam, please fill this form https://forms.gle/e8v6xKnxndigYELK9 by 6/7/2024) |
Assignments
You are strongly encouraged to watch this video before you start your first assignment.
Assignment #1
Assignment #2
Assignment #3
Assignment #4
Assignment #5
How am I doing?
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Other Policies
Integrity Policy
- Cheating WILL be taken seriously. Doing otherwise is not fair to honest students. It is also not fair to allow the cheater to thing that it is a reasonable alternative in life.
- Please review the UCR student handbook for more details on Academic Integrity.
- Anyone copying information or having information copied during a test will receive an F for the class and will not be allowed to drop. They will be reported to their college dean. If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean–I don’t want to be involved. Anyone caught cheating or falsely representing the work of others on the homework will not be allowed to turn in further homework. Your grade will be based exclusively on the tests with a penalty of 25% OR GREATER applied.
- We photocopy a random sampling of the exams in order to ensure that students do not modify their tests after they have been returned.
- Online solutions, etc.: A solutions manual exists for this text. Using it, or any solutions you may find on the internet elsewhere IS CHEATING and will be dealt with accordingly. We know what the solution manual solutions look like. Homework is a small fraction of your grade, so cheating on it is unproductive.
Public Health Regulation
- Masks are always required in the classroom.
- If you have any symptom of COVID-19 or seasonal flu, please stay at home.